1. Technical Field of the Invention
This invention relates generally to communication systems and more particularly to encoding/decoding of data within such communication systems.
2. Description of Related Art
Communication systems are known to transport large amounts of data between a plurality of end user devices. Such end user devices include telephones, facsimile machines, computers, television sets, cellular phones, personal digital assistants, et cetera. As is also known, such communication systems may be local area networks (LAN) and/or wide area networks (WAN). A local area network is generally understood to be a network that interconnects a plurality of end user devices distributed over a localized area (e.g., up to a radius of 10 kilometers). For example, a local area network may be used to interconnect workstations distributed within an office of a single building or a group of buildings, to interconnect Internet computer based equipment distributed around a factory or hospital, et cetera.
A wide area network is generally understood to be a network that covers a wide geographic area. Wide area networks include both public data networks and enterprise wide private data networks. A public data network is established and operated by a national network administrator specifically for data transmission. Such public data networks facilitate the interworkings of equipment from different manufacturers. Accordingly, standards by the ITU-T have been established for conveying data within public data networks. Currently, there are two main types of public data networks: packet switched public data networks and circuit switched public data networks. For example, the public switched telephone network is a circuit switched public data network while the Internet is a packet switched public data network. Other examples of wide area networks include integrated service digital networks (ISDN) and, broadband multi-service networks.
As is further known, communication systems may be networked together to yield larger communication systems, where such networking is typically referred to as internetworking. Internetworking is achieved via internetworking units that allow communication networks using the same or different protocols to be linked together. The internetworking units may be routers, gateways, protocol converters, bridges, and/or switches.
Regardless of the type of communication system (e.g., LAN, WAN, internetworking LAN and/or WAN), each communication system employs a data conveyance protocol to ensure that data is accurately conveyed within the system. All such data conveyance protocols are based on layers 1, 2, 3, and/or 4 of the open system interconnection (OSI) seven layer reference model. As is known, the layers include a physical layer (layer 1), a data link layer (layer 2), a network layer (layer 3), a transport layer (layer 4), a session layer, (layer 5), a presentation layer (layer 6), and an application layer (layer 7).
In general, a protocol is a formal set of rules and conventions that govern how each end user device and/or data terminal equipment (i.e., the infrastructure equipment of the communication system) exchanges information within the communication system. A wide variety of protocols exist, but can generally be categorized in the one of four types of protocols: a local area network protocol, a wide area network protocol, a routing protocol, or a network protocol. Local area network protocols operate at the physical and data link layers and define communication over various local area network and media. Wide area network protocols operate at the lowest three layers of the OSI model and define communication over the various wide area media. Routing protocols are network layer protocols that are responsible for path determination and traffic switching. Network protocols are the various upper layer protocols that exist in a given protocol suite. Examples of such protocols include asynchronous transfer mode (ATM), frame relay, TCP/IP, Ethernet, et cetera. Typically, such protocols include an encoding/decoding and/or scrambling/descrambling scheme. As is known, an encoding/decoding scheme enhances the reliability of data conveyances by encoding and/or scrambling data to include extra bits with the data to produce a code word. When the code word is received by the corresponding decoder and/or descrambler, it utilizes the extra bits to determine if the data was received without error. If the data was received without error, the decoder and/or descrambler uses the extra bits to determine and subsequently correct the error.
One such coding scheme is 8b/10b encoding, which, in general, takes 8-bits of input data and encodes it into a 10-bit code word. The basic concepts of 8b/10b encoding are disclosed in U.S. Pat. No. 4,486,739 (hereinafter referred to as the xe2x80x9c739 Patentxe2x80x9d). As taught in the 739 Patent, 8b/10b encoding is done in 2 parts: a 5-bit-to-6-bit part and a 3-bit-to-4-bit part. The 5-bit-to-6-bit part receives 5-bits of the 8-bit input data and a running disparity value. The 5-bit-to-6-bit part converts the 5-bits of input into a 6-bit code word based on the value of the 5-bits of input, the received running disparity, and an expected running disparity. In addition, the 5-bit-to-6-bit part generates an output running disparity for the 6-bit code word based on the value of the 5-bits of input and the received running disparity.
For example, as shown in Table I of the 739 Patent, the 5-bits of input are in the column labeled A, B, C, D and E, the expected running disparity is in the column labeled D-1, the 6-bit output is in the column labeled a, b, c, d, e, and i or the alternate column a, b, c, d, e and i, and the outputted running disparity is in the column labeled D0. For certain values of the 5-bits of input, the expected running disparity column includes an X, indicating a logical don""t-care, such that the 5-bits is always converted into the 6-bit code word of column a-i. Further, for such values of the 5-bits of input, the outputted running disparity equals the received running disparity. For instance, a 5-bit input of 10100 is encoded into 101001 and the outputted running disparity equals the received running disparity.
For the remainder of the values of the 5-bits of input, the 6-bit code word is from the lower case a-i column when the received running disparity equals the expected running disparity and the outputted running disparity is positive when the number of 1""s is greater than the number of 0""s in the 6-bit code word, is negative when the number of 1""s is less than the number of 0""s in the 6-bit code word, and equals the received running disparity when the number of 1""s equals the number of 0""s. If, however, the received running disparity does not equal the expected running disparity, the 6-bit code word is selected from the alternate lower case a-i column and the outputted running disparity is inverted. For example, if the 5-bits of input is equal to 00000, and the received running disparity equals the expected running disparity, then the 6-bit code word is 011000 and the outputted running disparity is negative. If, however, for the 5-bits of input equal to 00000, the received running disparity does not equal the expected running disparity, the 6-bit code word is 100111 and the outputted running disparity is positive.
The encoding of the 3-bits of input into a 4-bit code word is shown in Table II and functions in a similar way as the encoding of 5-bits into 6-bits. The received running disparity for the 3-bit-to-4-bit section is the outputted running disparity from the 5-bit-to-6-bit section and the outputted running disparity for the 8b/10b encoder corresponds to the running disparity outputted by the 3-bit-to-4-bit section. The decoding of a 10-bit code word, which is the combination of a 6-bit code word and a 4-bit code word, is shown in Tables IV and V and is essentially the same process as 8b/10b encoding but in reverse.
By utilizing the circuitry illustrated in the 739 Patent to generate the running disparities and implementing such circuitry on an integrated circuit using 0.18 micron CMOS technology, the propagation delay from receiving the running disparity to producing the output running disparity is approximately 5.1 nanoseconds. If the data rate for the 8-bit input is less than 196 megahertz (i.e., 1/5.1 nanoseconds), then the propagation delay to calculate the outputted running disparity is not a limiting factor in 8b/10b encoding. However, the calculation of the running disparity is a limiting factor for data rates over 196 megahertz and thus limits the maximum data rate for 8b/10b encoding utilizing the teachings of the 739 Patent to a maximum of 196 megahertz for an 8-bit input. Thus, if data rates greater than 196 megahertz are to be achieved, the propagation delay for calculating the running disparity must be decreased.
The running disparity calculation propagation delay is also a limitation when 8b/10b encoders are bonded together to achieve 16b/20b encoding, 24b/30b encoding, and/or 32b/40b encoding.
Therefore, a need exists for an improved method and apparatus of 8b/10b encoding/decoding that reduces the running disparity calculation time.
The 8b/10b encoding/decoding of the present invention substantially meets these needs and others. In one embodiment, 8b/10b encoding begins when an input running disparity is received. The processing then continues by receiving an 8-bit input that includes a 5-bit input portion and a 3-bit input portion. The processing then continues by determining, in parallel, a 6-bit running disparity (i.e., the outputted running disparity for the 5-bit to 6-bit part of an 8b/10b encoder) and a 4-bit running disparity (i.e., the outputted running disparity for the 3-bit to 4-bit part of an 8b/10b encoder). The 6-bit running disparity is based on a 1st possible 6-bit expected running disparity, a 2nd possible 6-bit expected running disparity, the input running disparity, and the 5-bit digital input portion. The 4-bit running disparity is based on the 1st possible 6-bit expected running disparity, the 2nd possible 6-bit expected running disparity, a 1st possible 4-bit expected running disparity, a 2nd possible 4-bit expected running disparity, the input running disparity and the 3-bit digital input portion. The processing then continues by determining a 6-bit output based on the 6-bit running disparity and the 5-bit input portion. The processing then continues by determining a 4-bit output based on the 4-bit running disparity and the 3-bit input portion. The resulting 10-bit encoded output is the combination of the 6-bit output and the 4-bit output. With such a method, and apparatus thereof, the calculation time for determining a running disparity is substantially reduced such that data rates in excess of 200 megahertz for 8-bit inputs can be readily achieved.
In another embodiment, parallel 8b/10b encoding may be achieved by initially receiving an N by 8-bit digital input, where the xe2x80x9cNxe2x80x9d indicates the number of 8b/10b encoders coupled in parallel, or bonded together. The processing continues by performing, in parallel, 8b/10b encoding of N 8-bit input values of the N by 8-bit input based on a plurality of running disparities for the N by 8-bit input. Each of the N 8-bit input values includes a 5-bit input portion and a 3-bit input portion. For example, if N corresponds to 4, such that four 8-bit/10-bit encoders are used, then each 8-bit/10-bit encoding process operates in parallel, with each receiving 8 bits of a 32-bit input. In addition, each 8-bit/10-bit encoding process produces its own running disparity and receives, as its input running disparity, the outputted running disparity from the preceding 8-bit/10-bit encoding process in a daisy-chain manner. The processing then continues by performing, in series, a running disparity calculation for each of the N 8-bit input values to produce the plurality of running disparities for the N by 8-bit digital input. The performing of the running disparity calculation for one of the running disparities includes determining, in parallel, a 6-bit running disparity and a 4-bit running disparity.
In another embodiment, decoding of an 8-bit/10-bit encoded data word begins by receiving a 10-bit encoded data word having a 6-bit section and a 4-bit section. The processing continues by receiving a running disparity. The processing then continues by determining, in parallel, a 6-bit running disparity and a 4-bit running disparity. The process then continues by determining a 5-bit decoded value based on the 6-bit running disparity in the 6-bit section. The processing then continues by determining a 3-bit decoded value based on the 4-bit running disparity in the 4-bit section. The 5-bit decoded value and the 3-bit decoded value provide an 8-bit decoded value.
In another embodiment, a method for parallel 8-bit/10-bit decoding begins by receiving an encoded N by 10-bit input, where N corresponds to the number of 8b/10b decoding processes coupled in parallel. The processing then proceeds by performing, in parallel, 8b/10b decoding of N 10-bit input values of the encoded N by 10-bit input based on a plurality of running disparities. The processing then continues by performing, in series, a running disparity calculation for each of the N 10-bit input values to produce the plurality of running disparities. The performance of a running disparity calculation that produces one of the plurality of running disparities includes determining, in parallel, a 4-bit running disparity and a 6-bit running disparity.
In any embodiment, the 8-bit/10-bit encoding/decoding and/or the parallel 8-bit/10-bit encoding/decoding in accordance with the present invention may be utilized within a multi-gigabit transceiver. Such-a multi-gigabit transceiver, or multiple multi-gigabit transceivers, may incorporated in a programmable logic device to provide a high-speed interface that transceive serial data in the multiple giga-bit-per-second (Gbps) range. This speed is achievable, at least in part, because the determination of the 6-bit running disparity and 4-bit running disparity are done in parallel, which substantially reduces the overall calculation time for producing a running disparity.